A ferroelectric memory stores data by use of polarization of a ferroelectric capacitor having hysteresis characteristics. A polarization direction is determined by controlling a direction of an electric field to be applied to the ferroelectric capacitor. For example, in order to write data “1” into the ferroelectric capacitor, electric potential on a bit line connected to one of electrodes of the ferroelectric capacitor is increased to a high level and electric potential on a plate line connected to the other electrode of the ferroelectric capacitor is decreased to a low level. On the other hand, in order to write data “0” into the ferroelectric capacitor, the electric potential on the bit line is decreased to a low level and the electric potential on the plate line is increased to a high level. The ferroelectric polarization direction is determined in this manner and thus either data “0” or data “1” is written into a memory cell.
In a reading operation, the electric potential on the bit line is decreased to the low level while the electric potential on the plate line is increased to the high level. Accordingly, charges corresponding to the ferroelectric polarization direction are transmitted to the bit line. A sense amplifier amplifies the electric potential on the bit line to read data. Since the ferroelectric memory is a destructive read-out type memory, the sense amplifier writes the read data back into the memory cell.
For an evaluation test of polarization characteristics of such a ferroelectric memory, a voltage is applied directly from outside to the bit line, and then an amount of signals (a difference in amount between signals “0” and “1”) in each memory cell is measured. In addition, to conduct a fatigue test for the ferroelectric memory, high-level and low-level voltages are alternately applied to the electrodes on both ends of the ferroelectric capacitor in a repeated manner. That is, the high-level and low-level voltages are alternately applied to the bit line and the plate line in a repeated manner. A test method for a semiconductor memory including these tests has been disclosed in Japanese Patent Application Publication No. 2002-313100.
According to the disclosed test method for a semiconductor memory, each bit line needs a transistor to connect the bit line with an external pad for the evaluation test of the polarization characteristics. Moreover, each bit line (or each pair of bit lines) also needs a circuit to apply a high-level or low-level voltage to the bit line for the fatigue test.
The evaluation test of the polarization characteristics of the ferroelectric capacitor and the fatigue test for the ferroelectric capacitor are necessary to ensure reliability of the ferroelectric memory. However, for the disclosed test method for a semiconductor memory, elements which are necessary for the evaluation test and the fatigue test need to be mounted in the memory. Such requirement has been one of obstacles to reducing a chip size of such a ferroelectric memory.